




Features
- Compliant with 100GBASE-ER4
- Support line rates from 103.125 Gbps to 111.81 Gbps
- Integrated LAN WDM TOSA / APD ROSA for up to 40 km reach
- Digital Diagnostics Monitoring Interface
- Duplex LC optical receptacle
- No external reference clock
- Electrically hot-pluggable
- Compliant with QSFP28 MSA with LC connector
- Case operating temperature range:0°C to 70°C
- Power dissipation < 4.0 W
Applications
- Ethernet 100GBASE-ER4 Lite
- ITU-T OTU4
- Fiber Channel
- Switch to Switch interface
- Switched backplane applications
- Router/Server interface
- Other optical transmission systems
Standard
- Compliant to IEEE 802.3ba
- Compliant with QSFP+ MSA
- Compliant to SFF-8436
Description
QSFP28-100G-ER4 is a 100Gbps transceiver module designed for optical communication applications compliant to Ethernet 100GBASE-ER4 Lite standard. The module converts 4 input channels of 25Gbps electrical data to 4 channels of LAN WDM optical signals and then multiplexes them into a single channel for 100Gbps optical transmission. Reversely on the receiver side, the module de-multiplexes a 100Gbps optical input into 4 channels of LAN WDM optical signals and then converts them to 4 output channels of electrical data.
The central wavelengths of the 4 LAN WDM channels are 1295.56, 1300.05, 1304.58 and 1309.14 nm as members of the LAN WDM wavelength grid defined in IEEE 802.3ba. The high performance cooled LAN WDM EA-DFB transmitters and high sensitivity APD receivers provide superior performance for 100Gigabit Ethernet applications up to 30km links without FEC and 40km links with FEC.
The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.
Specification
Absolute Maximum Ratings | ||||
Parameter | Symbol | Min | Max | Unit |
Storage Ambient Temperature | TSTG | -40 | 85 | ℃ |
Operating Humidity | HO | 5 | 95 | % |
Power Supply Voltage | Vcc | -0.5 | 3.6 | V |
Damage Threshold, each Lane | THd | -3 | dBm |
Recommended Operating Conditions | |||||
Parameter | Symbol | Min | Typical | Max | Unit |
Operating Case Temperature | Tc | 0 | 70 | ℃ | |
Power Supply Voltage | Vcc | 3.135 | 3.3 | 3.465 | V |
Power Supply Current | ICC | 1200 | mA | ||
Data Rate,each Lane | 25.78125 | Gbps | |||
Control Input Voltage High | 2 | Vcc | V | ||
Control Input Voltage Low | 0 | 0.8 | V | ||
Data Rate Accuracy | -100 | 100 | ppm | ||
Link Distance with G.652 (without FEC) | D1 | - | 30 | km |
Electrical transmitter Characteristics | ||||||||||
Parameter | Symbol | Min | Typical | Max | Unit | Notes | ||||
Power Consumption | 4.5 | W | ||||||||
Overload Differential Voltage pk-pk | TP1a | 900 | mV | |||||||
Common Mode Voltage (Vcm) | TP1 | -350 | 2850 | mV | ||||||
Differential Termination Resistance Mismatch | TP1 | 10 | % | |||||||
Differential Return Loss (SDD11) | TP1 | See CEI- 28G-VSR Equation 13-19 | dB | |||||||
Common Mode to Differential conversion and Differential to Common Mode conversion (SDC11, SCD11) | TP1 | See CEI- 28G-VSR Equation 13-20 | dB | |||||||
Stressed Input Test | TP1a | See CEI- 28G-VSR Section 13.3.11.2.1 | ||||||||
Electrical receiver Characteristics | ||||||||||
Parameter | Symbol | Min | Typical | Max | Unit | Notes | ||||
Differential Voltage, pk-pk | TP4 | 900 | mV | |||||||
Common Mode Voltage (Vcm) | TP4 | -350 | 2850 | mV | ||||||
Common Mode Noise, RMS | TP4 | 17.5 | mV | |||||||
Differential Termination Resistance Mismatch | TP4 | 10 | % | |||||||
Differential Return Loss (SDD11) | TP4 | See CEI- 28G-VSR Equation 13-19 | dB | |||||||
Common Mode to Differential conversion and Differential to Common Mode conversion (SDC22, SCD22) | TP4 | See CEI- 28G-VSR Equation 13-21 | dB | |||||||
Common Mode Return Loss (SCC22) | TP4 | -2 | dB | |||||||
Transition Time, 20 to 80% | TP4 | 9.5 | ps | |||||||
Vertical Eye Closure (VEC) | TP4 | 5.5 | dB | |||||||
Eye Width at 10-15 probability (EW15) | tr | 0.57 | UI | |||||||
Eye Height at 10-15 probability (EH15) | tf | 228 | mV | |||||||
Optical transmitter Characteristics | ||||||||||
Parameter | Symbol | Min | Typical | Max | Unit | Notes | ||||
Launched Power (avg.) | Pavg | -2.9 | 4.5 | dBm | ||||||
Total Output. Power | Pout | 10.5 | dBm | |||||||
OMA, each Lane | POMA | 0.1 | 4.5 | dBm | ||||||
Difference in Launch Power between any Two Lanes (OMA) | Ptx,diff | 3.6 | dB | |||||||
Launch Power in OMA minus Transmitter and Dispersion Penalty (TDP), each Lane | -0.65 | dBm | ||||||||
Wavelength Assignment | λ0 | 1294.53 | 1295.56 | 1296.59 | nm | |||||
λ1 | 1299.02 | 1300.05 | 1301.09 | |||||||
λ2 | 1303.54 | 1304.58 | 1305.63 | |||||||
λ3 | 1308.09 | 1309.14 | 1310.19 | |||||||
TDP, each Lane | TDP | 2.5 | dB | |||||||
Spectral Width(-20dB) | ∆λ | 1 | nm | |||||||
Side Mode Suppression Ratio | SMSR | 30 | dB | |||||||
Extinction Ratio | ER | 7 | dB | |||||||
Transmitter OFF Output Power | POff | -30 | dBm | |||||||
RIN20 OMA | RIN | -130 | Ohm | |||||||
Output Eye Mask definition {X1,X2,X3,Y1,Y2,Y3} | {0.25,0.4,0.45,0.25,0.28,0.4} |
Optical receiver Characteristics | |||||||
Parameter | Symbol | Min | Typical | Max | Unit | Notes | |
Damage Threshold, each Lane | THd | -3 | dBm | ||||
Average Receive Power, each Lane | -16.9 | -4.9 | dBm | @30km | |||
Average Receive Power, each Lane | -20.9 | -4.9 | dBm | @30km | |||
Receive Power (OMA), each Lane | -1.9 | dBm | |||||
Receiver Sensitivity (OMA), each Lane | SEN1 | -14.65 | dBm | For BER = 1x10-12 | |||
Stressed Receiver Sensitivity (OMA), each Lane | -12.5 | dBm | For BER = 1x10-12 | ||||
Receiver Sensitivity (OMA), each Lane | SEN2 | -18.65 | dBm | For BER =5x10-5 | |||
Stressed Receiver Sensitivity (OMA), each Lane | -16.65 | dBm | For BER =5x10-5 | ||||
Receiver reflectance | -26 | dB | |||||
Difference in Receive Power between any Two Lanes (Average and OMA) | Ptx,diff | 3.6 | dB | ||||
LOS Hysteresis | LOSH | 0.5 | dB | ||||
LOS | Optical De-assert | Pd | -24 | dBm | |||
Optical Assert | Pa | -26 | |||||
Receiver Electrical 3 dB upper Cutoff Frequency, each Lane | Fc | 31 | GHz | ||||
Vertical Eye Closure Penalty, each Lane | 1.5 | dB | |||||
Stressed Eye J2 Jitter, each Lane | 0.3 | UI | |||||
Stressed Eye J9 Jitter, each Lane | 0.47 | UI |
Pin Definition
Figure1 QSFP MSA-compliant 38-pin connector
Pin | Symbol | Name/Description | Notes |
1 | GND | Transmitter Ground(Common with Receiver Ground) | 1 |
2 | TX2N | Transmitter Inverted Data Input | |
3 | TX2P | Transmitter Non-Inverted Data Output | |
4 | GND | Ground | 1 |
5 | TX4N | Transmitter Inverted Data Input | |
6 | TX4P | Transmitter Non-Inverted Data Output | |
7 | GND | Ground | 1 |
8 | ModSelL | Module Select | |
9 | ResetL | Module Reset | |
10 | Vcc Rx | +3.3 V Power supply receiver | 2 |
11 | SCL | 2-wire serial interface clock | |
12 | SDA | 2-wire serial interface data | |
13 | GND | Ground | |
14 | RX3P | Receiver Non-Inverted Data Output | |
15 | RX3N | Receiver Inverted Data Output | |
16 | GND | Ground | 1 |
17 | RX1P | Receiver Non-Inverted Data Output | |
18 | RX1N | Receiver Inverted Data Output | |
19 | GND | Ground | 1 |
20 | GND | Ground | 1 |
21 | RX2N | Receiver Inverted Data Output | |
22 | RX2P | Receiver Non-Inverted Data Output | |
23 | GND | Ground | 1 |
24 | RX4N | Receiver Inverted Data Output | 1 |
25 | RX4P | Receiver Non-Inverted Data Output | |
26 | GND | Ground | 1 |
27 | ModPrsL | Module Present | |
28 | IntL | Interrupt | |
29 | Vcc Tx | +3.3 V Power supply transmitter | 2 |
30 | Vcc1 | +3.3 V Power Supply | 2 |
31 | LPMode | Low Power Mode | |
32 | GND | Ground | 1 |
33 | TX3P | Transmitter Non-Inverted Data Input | |
34 | TX3N | Transmitter Inverted Data Output | |
35 | GND | Ground | 1 |
36 | TX1P | Transmitter Non-Inverted Data Input | |
37 | TX1N | Transmitter Inverted Data Output | |
38 | GND | Ground | 1 |
Table 1: QSFP Module PIN Definition
Notes:
1. GND is the symbol for signal and supply (power) common for QSFP28 modules. All are common within the QSFP28 module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown in Figure 3 below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP28 transceiver module in any combination. The connector pins are each rated for a maximum current of 1000mA.
Recommended Power Supply Filter
Functional Description
The transceiver module receives 4 channels of 25Gbpselectrical data, which are processed by a 4-channel Clock and Data Recovery (CDR) IC that reshapes and reduces the jitter of each electrical signal. Subsequently, EML laser driver IC converts each one of the 4 channels of electrical signals to an optical signal that is transmitted from one of the 4 cooled EML lasers which are packaged in the Transmitter Optical Sub-Assembly (TOSA). Each laser launches the optical signal in specific wavelength specified in IEEE 802.3ba 100GBASE-ER4 requirements. These 4-lane optical signals will be optically multiplexed into a single fiber by a 4-to-1 optical WDM MUX. The optical output power of each channel is maintained constant by an automatic power control (APC) circuit. The transmitter output can be turned off by TX_DIS hardware signal and/or 2-wire serial interface.
The receiver receives 4-lane LAN WDM optical signals. The optical signals are de-multiplexed by a 1-to-4 optical DEMUX and each of the resulting 4 channels of optical signals is fed into one of the 4 receivers that are packaged into the Receiver Optical Sub-Assembly (ROSA). Each receiver converts the optical signal to an electrical signal. The regenerated electrical signals are retimed and de-jittered and amplified by the RX portion of the 4-channel CDR. The retimed 4-lane output electrical signals are compliant with CEI-28G-VSR interface requirements. In addition, each received optical signal is monitored by the DOM section. The monitored value is reported through the 2-wire serial interface. If one or more received optical signal is weaker than the threshold level, RX_LOS hardware alarm will be triggered.
A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and VccRx are internally connected and should be applied concurrently. As per MSA specifications the module offers 7 low speed hardware control pins (including the 2-wire serial interface): ModSelL, SCL, SDA, ResetL, LPMode, ModPrsL and IntL.
Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire serial communication commands. The ModSelL allows the use of this product on a single 2-wire interface bus – individual ModSelL lines must be used.
Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the QSFP28 memory map.
The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.
Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order to protect hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted.
Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.
Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.
Transceiver Block Diagram
Regulatory Compliance
Feature | Test | Method |
Electrostatic Discharge (ESD) to the Electrical Pins | MIL-STD-883E Method 3015.7 | Class 1(>1000V for SFI pins, >2000Vfor other pins.) |
Electrostatic Discharge (ESD) Immunity | IEC61000-4-2 | Class 2(>4.0kV) |
Electromagnetic Interference (EMI) | CISPR22 ITE Class B FCC Class B CENELEC EN55022 VCCI Class 1 | Comply with standard |
Immunity | IEC61000-4-3 | Comply with standard |
Eye Safety | FDA 21CFR 1040.10 and 1040.11 EN (IEC) 60825-1,2 | Compatible with Class I laser Product |
Ordering information
Model No. | Product Description |
QSFP28-100G-ER4 | QSFP28 100G SM 40KM ER4 |