CWDM Module
CWDM Module
CWDM Module

CWDM Module

Model NO.
QSFP28-100G-CWDM4
Delivery:
FOB/EXW
Minimum order quantity:
1 piece
Supply Ability:
5000 piece / Day
Country of Origin:
CHINA
Stock Time:
3-5 Days
Quantity:

Features

  • Transmission data rate up to 25.78Gbps per channel
  • 4 channels full-duplex transceiver modules
  • 4 x 26Gb/s DFB-based CWDM uncooled transmitter
  • 4 channels PIN ROSA
  • Internal CDR circuits on both receiver and transmitter channels
  • Duplex LC optical receptacle
  • Built- in digital diagnostic functions
  • Hot Pluggable QSFP form factor
  • Up to reach 2km for G.652 SMF
  • Compliant with QSFP28 MSA with LC connector
  • Commercial operating case temperature range: -5ºC to 70ºC
  • RoHS-6 Compliant
  • Power dissipation < 3.5 W

Applications

  • Data Center Interconnect
  • 100G CWDM4 applications
  • Infiniband EDR interconnects
  • Enterprise networking

Standard

  • Compliant to IEEE 802.3ba, IEEE 802.3bm
  • Compliant with SFP MSA
  • Compliant to SFF-8436

Description

QSFP28-100G-CWDM4 transceiver module designed for optical communication applications compliant with the QSFP MSA,CWDM4 MSA and portions of IEEE P802.3bm standard. The module converts 4 input channels of 25Gb/s electrical data to 4 channels of CWDM optical signals and then multiplexes them into a single channel for 100Gb/s optical transmission. Reversely on the receiver side, the module de-multiplexes a 100Gb/s optical input into 4 channels of CWDM optical signals and then converts them to 4 output channels of electrical data.

The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in CWDM4 MSA. The high performance Uncooled CWDM DFB transmitters and high sensitivity PIN receivers provide superior performance for 100Gigabit E thernet applications up to 2km links.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

Specification:

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Storage Ambient Temperature

TSTG

-40

85

Operating Humidity

HO

5

95

%

Power Supply Voltage

Vcc

-0.3

4

V

Signal Input Voltage

Vcc-0.3

Vcc +0.3

V

Damage Threshold, each Lane

TH

5.5

dBm

Recommended Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

Operating Case Temperature

Tc

-5

70

Power Supply Voltage

Vcc

3.135

3.3

3.465

V

Power Supply Current

Icc

1060

mA

Data Rate,each Lane

25.78125

Gbps

Link Distance with G.652

D

-

2

-

km

Optical transmitter Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Launched Power (avg.)

Pavg

-6.5

2.5

dBm

Total Output. Power

Pout

8.5

dBm

OMA, each Lane

POMA

-4

2.5

dBm

TDP, each Lane

TDP

3

dB

Wavelength Assignment

λ0

1294.53

1295.56

1296.59

nm

λ1

1299.02

1300.05

1301.09

λ2

1303.54

1304.58

1305.63

λ3

1308.09

1309.14

1310.19

Spectral Width(-20dB)

∆λ

1

nm

Side Mode Suppression Ratio

SMSR

30

dB

Extinction Ratio

ER

3

dB

Transmitter OFF Output Power

POff

-30

dBm

Differential Line InputImpedance

RIN

-130

Ohm

Output Eye Mask definition

{X1X2X3Y1Y2Y3}

{0.310.40.450.340.380.4}

Output Eye Diagram

Compliant with IEEE802.3ae eye mask

OpticalreceiverCharacteristics

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Receiver Sensitivity

S

-10.0

dBm

1

Stressed Receiver Sensitivity

(OMA),each Lane

-7.3

dBm

Average Receive Power, each

lane

-11.5

2.5

dBm

Receive Power (OMA),

each lane

2.5

dBm

ReceiverElectrical 3 dBupper Cutoff Frequency, eachFc Lane

FC

31

GHz

Optical Power Input Overload

Pin-max

4.5

dBm

LOS

Optical De-assert

Pd

-14

dBm

Optical Assert

Pa

-16

LOS Hysteresis

LOSH

0.5

2

dB

Vertical Eye Closure Penalty

VECP

1.9

dB

Stressed Eye J2 Jitter

J2

0.33

UI

Stressed Eye J4 Jitter

J4

0.48

UI

Notes:

  1. Measured with a PRBS 231-1 test pattern, @25.78Gb/s, BER<5x10-5.

Pin Definition

Figure1 QSFP MSA-compliant 38-pin connector

Pin

Symbol

Name/Description

Notes

1

GND

Transmitter Ground(Common with Receiver Ground)

1

2

TX2N

Transmitter Inverted Data Input

3

TX2P

Transmitter Non-Inverted Data Input

4

GND

Ground

1

5

TX4N

Transmitter Inverted Data Input

6

TX4P

Transmitter Non-Inverted Data Input

7

GND

Ground

1

8

ModSelL

Module Select

9

ResetL

Module Reset

10

Vcc Rx

+3.3 V Power supply receiver

2

11

SCL

2-wire serial interface clock

12

SDA

2-wire serial interface data

13

GND

Ground

14

RX3P

Receiver Non-Inverted Data Output

15

RX3N

Receiver Inverted DataOutput

16

GND

Ground

1

17

RX1P

Receiver Non-Inverted Data Output

18

RX1N

Receiver Inverted DataOutput

19

GND

Ground

1

20

GND

Ground

1

21

RX2N

Receiver Inverted DataOutput

22

RX2P

Receiver Non-Inverted Data Output

23

GND

Ground

1

24

RX4N

Receiver Inverted DataOutput

1

25

RX4P

Receiver Non-Inverted Data Output

26

GND

Ground

1

27

ModPrsL

Module Present

28

IntL

Interrupt

29

Vcc Tx

+3.3 V Power supply transmitter

2

30

Vcc1

+3.3 V Power Supply

2

31

LPMode

Low Power Mode

32

GND

Ground

1

33

TX3P

Transmitter Non-Inverted Data Input

34

TX3N

Transmitter Inverted Datainput

35

GND

Ground

1

36

TX1P

Transmitter Non-Inverted Data Input

37

TX1N

Transmitter Inverted Datainput

38

GND

Ground

1

Table 1: QSFP Module PIN Definition

Notes

1. Module circuit ground is isolated from module chassis ground within the module.

2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15Vand 3.6V.

Digital Diagnostic Functions

It support the 2-wire serial communication protocol as defined in the QSFP28 MSA. Which allows real-time access to the following operatingparameters:

  • ​​​Transceiver temperature
  • Laser bias current
  • Transmitted optical power
  • Received optical power
  • Transceiver supply voltage

It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range.

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 -QSFP28 Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.

For more detailed information including memory map definitions, please see the QSFP28 MSA Specification.

Regulatory Compliance

Feature

Test

Method

Electrostatic Discharge

(ESD) to the Electrical Pins

MIL-STD-883E

Method 3015.7

Class 1(>1000V for SFI pins, >2000Vfor other pins.)

Electrostatic Discharge

(ESD) Immunity

IEC61000-4-2

Class 2(>4.0kV)

Electromagnetic

Interference (EMI)

CISPR22 ITE Class B

FCC Class B

CENELEC EN55022

VCCI Class 1

Comply with standard

Immunity

IEC61000-4-3

Comply with standard

Eye Safety

FDA 21CFR 1040.10 and

1040.11

EN (IEC) 60825-1,2

Compatible with Class I laser

Product

Ordering information

Model No.

Product Description

QSFP28-100G-CWDM4

QSFP28 100Gbps CWDM4 2km

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