CWDM Module

Features

• Transmission data rate up to 25.78Gbps per channel
• 4 channels full-duplex transceiver modules
• 4 x 26Gb/s DFB-based CWDM uncooled transmitter
• 4 channels PIN ROSA
• Internal CDR circuits on both receiver and transmitter channels
• Duplex LC optical receptacle
• Built- in digital diagnostic functions
• Hot Pluggable QSFP form factor
• Up to reach 2km for G.652 SMF
• Compliant with QSFP28 MSA with LC connector
• Commercial operating case temperature range: -5ºC to 70ºC
• RoHS-6 Compliant
• Power dissipation < 3.5 W

Applications

• Data Center Interconnect
• 100G CWDM4 applications
• Infiniband EDR interconnects
• Enterprise networking

Standard

• Compliant to IEEE 802.3ba, IEEE 802.3bm
• Compliant with SFP MSA
• Compliant to SFF-8436

Description

QSFP28-100G-CWDM4 transceiver module designed for optical communication applications compliant with the QSFP MSA,CWDM4 MSA and portions of IEEE P802.3bm standard. The module converts 4 input channels of 25Gb/s electrical data to 4 channels of CWDM optical signals and then multiplexes them into a single channel for 100Gb/s optical transmission. Reversely on the receiver side, the module de-multiplexes a 100Gb/s optical input into 4 channels of CWDM optical signals and then converts them to 4 output channels of electrical data.

The central wavelengths of the 4 CWDM channels are 1271, 1291, 1311 and 1331 nm as members of the CWDM wavelength grid defined in CWDM4 MSA. The high performance Uncooled CWDM DFB transmitters and high sensitivity PIN receivers provide superior performance for 100Gigabit E thernet applications up to 2km links.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

Specification:

Notes:

1. Measured with a PRBS 2³¹-1 test pattern, @25.78Gb/s, BER<5x10-⁵.

Pin Definition

Figure1 QSFP MSA-compliant 38-pin connector

Table 1: QSFP Module PIN Definition

Notes：

1. Module circuit ground is isolated from module chassis ground within the module.

2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15Vand 3.6V.

Digital Diagnostic Functions

It support the 2-wire serial communication protocol as defined in the QSFP28 MSA. Which allows real-time access to the following operatingparameters:

• ​​​Transceiver temperature
• Laser bias current
• Transmitted optical power
• Received optical power
• Transceiver supply voltage

It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range.

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 -QSFP28 Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.

For more detailed information including memory map definitions, please see the QSFP28 MSA Specification.

Regulatory Compliance

Ordering information