QSFP28-100G-LR4
QSFP28-100G-LR4
QSFP28-100G-LR4

QSFP28-100G-LR4

Model NO.
QSFP28-100G-LR4
Delivery:
FOB/EXW
Minimum order quantity:
1 piece
Supply Ability:
5000 piece / Day
Country of Origin:
CHINA
Stock Time:
3-5 Days
Quantity:

Features

  • Support line rates from 103.125 Gbps to 111.81 Gbps
  • Digital Diagnostics Monitoring Interface
  • Duplex LC optical receptacle
  • Integrated LAN WDM TOSA / ROSA for up to 10 km reach over SMF

  • Hot Pluggable
  • No external reference clock
  • Compliant with QSFP28 MSA with LC connector
  • Commercial operating case temperature range: -5ºC to 70ºC
  • RoHS-6 Compliant
  • Power dissipation < 3.5 W

Applications

  • 100G Ethernet &100GBASE-LR4
  • Fiber Channel
  • Switch to Switch interface
  • Switched backplane applications
  • Router/Server interface
  • Other optical transmission systems

Standard

  • Compliant to IEEE 802.3ba, IEEE 802.3bm and 100G LR4
  • Compliant with SFP MSA
  • Compliant to SFF-8436

Description

QSFP28-100G-LR4Optical Transceiver integrates receiver and transmitter path on one module. In the transmit side, four lanes of serial data streams are recovered, retimed, and passed to four laser drivers. The laser drivers control 4- Distributed Feedback Laser (DFB) with center wavelength of 1296 nm, 1300nm, 1305nm and 1309 nm. The optical signals are multiplexed to a single –mode fiber through an industry standard LC connector. In the receive side, the four lanes of optical data streams are optically de-multiplexed by the integrated optical de-multiplexer. Each data stream is recovered by a PIN photo-detector and trans-impedance amplifier, retimed. This module features a hot-pluggable electrical interface, low power consumption and MDIO management interface.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP28 Multi-Source Agreement (MSA) and compliant to IEEE 802.3bm.

Specification:

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Storage Ambient Temperature

TSTG

-40

85

Operating Humidity

HO

5

95

%

Power Supply Voltage

Vcc

-0.3

4

V

Signal Input Voltage

Vcc-0.3

Vcc +0.3

V

Recommended Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

Operating Case Temperature

Tc

-5

70

Power Supply Voltage

Vcc

3.135

3.3

3.465

V

Power Supply Current

ICC

1060

mA

Data Rate,each Lane

25.78125

Gbps

Fiber Length 9/125μm core SMF

-

10

-

km

Optical transmitter Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Launched Power (avg.)

Pavg

-4.3

4.5

dBm

Total Output. Power

Pout

10.5

dBm

Wavelength Assignment

λ0

1294.53

1295.56

1296.59

nm

λ1

1299.02

1300.05

1301.09

λ2

1303.54

1304.58

1305.63

λ3

1308.09

1309.14

1310.19

Spectral Width(-20dB)

∆λ

1

nm

Side Mode Suppression Ratio

SMSR

30

dB

Extinction Ratio

ER

4

dB

Transmitter OFF Output Power

POff

-30

dBm

Differential Line InputImpedance

RIN

-128

Ohm

Output Eye Mask definition

{X1X2X3Y1Y2Y3}

{0.250.40.450.250.280.4}

Output Eye Diagram

Compliant with ITU-T G.957 eye mask and IEEE802.3ae eye mask

OpticalreceiverCharacteristics

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Receiver Sensitivity

S

-10.6

dBm

1

Optical Power Input Overload

Pin-max

4.5

dBm

LOS

Optical De-assert

LOSD

-12

dBm

Optical Assert

LOSA

-30

Receiver Reflectance

Rr

-26

dB

Notes:

  1. Measured with a PRBS 231-1 test pattern, @25.78Gb/s, BER<10-12.

Pin Definition

Figure1 QSFP MSA-compliant 38-pin connector

Pin

Symbol

Name/Description

Notes

1

GND

Transmitter Ground(Common with Receiver Ground)

1

2

TX2N

Transmitter Inverted Data Input

3

TX2P

Transmitter Non-Inverted Data Input

4

GND

Ground

1

5

TX4N

Transmitter Inverted Data Input

6

TX4P

Transmitter Non-Inverted Data Input

7

GND

Ground

1

8

ModSelL

Module Select

9

ResetL

Module Reset

10

Vcc Rx

+3.3 V Power supply receiver

2

11

SCL

2-wire serial interface clock

12

SDA

2-wire serial interface data

13

GND

Ground

14

RX3P

Receiver Non-Inverted Data Output

15

RX3N

Receiver Inverted DataOutput

16

GND

Ground

1

17

RX1P

Receiver Non-Inverted Data Output

18

RX1N

Receiver Inverted DataOutput

19

GND

Ground

1

20

GND

Ground

1

21

RX2N

Receiver Inverted DataOutput

22

RX2P

Receiver Non-Inverted Data Output

23

GND

Ground

1

24

RX4N

Receiver Inverted DataOutput

1

25

RX4P

Receiver Non-Inverted Data Output

26

GND

Ground

1

27

ModPrsL

Module Present

28

IntL

Interrupt

29

Vcc Tx

+3.3 V Power supply transmitter

2

30

Vcc1

+3.3 V Power Supply

2

31

LPMode

Low Power Mode

32

GND

Ground

1

33

TX3P

Transmitter Non-Inverted Data Input

34

TX3N

Transmitter Inverted Datainput

35

GND

Ground

1

36

TX1P

Transmitter Non-Inverted Data Input

37

TX1N

Transmitter Inverted Datainput

38

GND

Ground

1

Table 1: QSFP Module PIN Definition

Notes

1. GND is the symbol for signal and supply (power) common for QSFP28 modules. All are common within the QSFP28 module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.

2. VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown in Figure 3 below. Vcc Rx, Vcc1 and Vcc Tx may be internally connected within the QSFP28 transceiver module in any combination. The connector pins are each rated for a maximum current of 500mA.

Digital Diagnostic Functions

QSFP28-100G-LR4 support the 2-wire serial communication protocol as defined in the QSFP28 MSA. Which allows real-time access to the following operatingparameters:

  • Transceiver temperature
  • Laser bias current
  • Transmitted optical power
  • Received optical power
  • Transceiver supply voltage

It also provides a sophisticated system of alarm and warning flags, which may be used to alert end-users when particular operating parameters are outside of a factory-set normal range.

The operating and diagnostics information is monitored and reported by a Digital Diagnostics Transceiver Controller inside the transceiver, which is accessed through the 2-wire serial interface. When the serial protocol is activated, the serial clock signal (SCL pin) is generated by the host. The positive edge clocks data into the QSFP28 transceiver into those segments of its memory map that are not write-protected. The negative edge clocks data from the QSFP28 transceiver. The serial data signal (SDA pin) is bi-directional for serial data transfer. The host uses SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories are organized as a series of 8-bit data words that can be addressed individually or sequentially. The 2-wire serial interface provides sequential or random access to the 8 bit parameters, addressed from 00h to the maximum address of the memory.

This clause defines the Memory Map for QSFP28 transceiver used for serial ID, digital monitoring and certain control functions. The interface is mandatory for all QSFP28 devices. The memory map has been changed in order to accommodate 4 optical channels and limit the required memory space. The structure of the memory is shown in Figure 2 -QSFP28 Memory Map. The memory space is arranged into a lower, single page, address space of 128 bytes and multiple upper address space pages. This structure permits timely access to addresses in the lower page, e.g. Interrupt Flags and Monitors. Less time critical entries, e.g. serial ID information and threshold settings, are available with the Page Select function. The structure also provides address expansion by adding additional upper pages as needed. For example, in Figure 2 upper pages 01 and 02 are optional. Upper page 01 allows implementation of Application Select Table, and upper page 02 provides user read/write space. The lower page and upper pages 00 and 03 are always implemented. The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order to enable a “one-time-read” for all data related to an interrupt situation. After an Interrupt, IntL, has been asserted, the host can read out the flag field to determine the effected channel and type of flag.

For more detailed information including memory map definitions, please see the QSFP28 MSA Specification.

Regulatory Compliance

Feature

Test

Method

Electrostatic Discharge

(ESD) to the Electrical Pins

MIL-STD-883E

Method 3015.7

Class 1(>1000V for SFI pins, >2000Vfor other pins.)

Electrostatic Discharge

(ESD) Immunity

IEC61000-4-2

Class 2(>4.0kV)

Electromagnetic

Interference (EMI)

CISPR22 ITE Class B

FCC Class B

CENELEC EN55022

VCCI Class 1

Comply with standard

Immunity

IEC61000-4-3

Comply with standard

Eye Safety

FDA 21CFR 1040.10 and

1040.11

EN (IEC) 60825-1,2

Compatible with Class I laser

Product

Ordering information

Model No.

Product Description

QSFP28-100G-LR4

QSFP28 100Gbps SM 10KM LR4

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